artikel:ipc:mac7116

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artikel:ipc:mac7116 [Mon. 01.04.2019 04:11] – go4itartikel:ipc:mac7116 [Wed. 10.11.2021 19:35] – [MAC7116 MCU] go4it
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 ====== MAC7116 MCU ====== ====== MAC7116 MCU ======
  
-===== Data =====+{{:artikel:ipc:mac7116_on_pcb.jpg?direct&320|}} {{:artikel:ipc:mac7116_pinout.png?direct&320|}} 
 +===== Markings =====
  
-  * Bauteileschriftung: ''NXP MAC7116VAG50'' +  - ''MAC7116'' = Product 
-  * Gehäuse: 144LQFP +  - ''V'' = Temperature range -40°C to +105°C 
-  * Core: ARM7TDMI-S: +  - ''AG'' = LQFP-144 Package 
-    * 32 Bit Big-Endian +  - ''50'' = Core Speed 50 MHz 
-    * ARMv4 Instruction-Set +  - ''L38Y'' = Mask Set "Fully-qualified, production"
-    * 50 MHz +
-    * 8kb unified cache +
-    * Memory Management Unit (MMU) +
-  * Quartz: 8 MHz +
-  * Program Flash: 1 MByte +
-  * Data Flash: 48 KByte +
-  * SRAM: 32 KByte +
-  * Datenblatt: [[https://www.nxp.com/part/MAC7116VAG50]]+
  
-{{:artikel:ipc:mac7116_pinout.png?direct|}} 
  
-==== Bootstrap ====+===== Specifications =====
  
-=== Chip operation mode ===+  * 1 MByte of Program Flash 
 +  * 32 KByte of Data Flash 
 +  * 48 KBytes of SRAM 
 +  * External Bus 
 +  * 1x ATD Module A (AD-Converter with 16 Channels and 8/10-bit resolution) 
 +  * 4x CAN Modules (A, B, C and D) 
 +  * 4x eSCI Modules (A, B, C and D) 
 +  * 2x DSPI Modules (A and B) 
 +  * I2C Module 
 +  * eMIOS Module, 16 channels, 16-bit 
 +  * Timer Module, 10 channels, 24-bit 
 +  * 112 GPIO Ports (Total)
  
-The chip operating mode is determined by the states of the MODA (Pin 71) and MODB (Pin 70) pins at reset and the security status of the program Flash.+===== Operating ===== 
 + 
 +==== Bootstrap ====
  
-{{:artikel:ipc:convers_vfl_mcu-area_explained.jpg?direct&400|}}+As of the wirering of MODA and MODB pins, the chip is running in "Normal Single Chip Mode". This means:
  
-^ MODA ^ MODB ^ Program Flash secured ^ Chip mode ^ Description ^ +  - All debug features available (JTAG, for example) 
-|  0  |  0  |  No  | Normal Single-Chip Mode | Boots from internal flash | +  — The chips boots from program Flash
-|  0  |  1  |  No  | Normal Expanded Mode | Boots from external flash | +
-|  1  |  0  |  No  | Normal Data Flash Boot Mode | Boots from data flash | +
-|  0  |  0  |  Yes  | Secured Single-Chip Mode | Boots from internal flash | +
-|  0  |  1  |  Yes  | Secured Expanded Mode | Boots from external flash | +
-|  1  |  0  |  Yes  | Secured Data Flash Boot Mode | Boots from data flash | +
-|  1  |  1  |  -  | -RESERVED - |+
  
 === Memory Map === === Memory Map ===
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 ^ Periphal ^ Base-Addr ^ End-Addr ^ Size ^ ^ Periphal ^ Base-Addr ^ End-Addr ^ Size ^
 | Program Flash | 0x0000 0000 | 0x000F FFFF | 0x10 0000 (1 mb) | | Program Flash | 0x0000 0000 | 0x000F FFFF | 0x10 0000 (1 mb) |
-| Data Flash | 0xFE00 0000 |  | (48 kb) | +| Data Flash | 0xFE00 0000 |  | (32 kb) | 
-| SRAM  | 0x4000 0000 | 0x4000 7FFF | 0x8000 (32 kb) |+| SRAM  | 0x4000 0000 | 0x4000 7FFF | 0x8000 (48 kb) |
  
 progflash base 0xfc100000 progflash base 0xfc100000
Zeile 106: Zeile 105:
  
 https://www.nxp.com/part/MAC7116VAG50 https://www.nxp.com/part/MAC7116VAG50
 +
 +=== DEFs ===
  
 <code> <code>
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 cfmdfdacc       MM 0xFC0F0046 8 cfmdfdacc       MM 0xFC0F0046 8
 </code> </code>
 +
 +=== Segger ===
  
 <code> <code>
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 mem16 fe000000,1 // verify writing->FE000000=FFFF // write fault mem16 fe000000,1 // verify writing->FE000000=FFFF // write fault
 </code> </code>
 +
 +=== PEEDI ===
 +
 +<code>
 +;-------------------------------------------------------------------------------
 +;
 +;
 +;   PEEDI target configuration file for Freescale MAC7100 processor
 +;
 +;   Ronetix
 +;
 +;   Supported devices   : MAC7100
 +;
 +;   Revision            : 1.5
 +;
 +;   Date                : March 23, 2007
 +;
 +; The software is delivered "AS IS" without warranty or condition of any
 +; kind, either express, implied or statutory. This includes without
 +; limitation any warranty or condition with respect to merchantability or
 +; fitness for any particular purpose, or against the infringements of
 +; intellectual property rights of others.
 +;
 +;-------------------------------------------------------------------------------
 +
 +;--------------------------------------------------------------------------
 +; The following section contains licenses that are required for PEEDI to
 +; operate. These licenses must be filled before using this file.
 +; The [LICENSE] section may contain license keys for one or more PEEDIs.
 +;
 +;   Example:
 +;       [LICENSE]
 +;       KEY         = UPDATE_24MAY2010, 1111-1111-1111-1
 +;       KEY         = XXXXX, 2222-2222-2222-2
 +;
 +; The [LICENSE] section may point to an external file which contains
 +; license keys for one or more PEEDIs. The external file must include 
 +; the text [LICENSE] followed by all keys.
 +;
 +;   Example:
 +; [LICENSE]
 +; FILE = tftp://192.168.3.1/license.txt
 +; or
 +; FILE=eep:license.txt 
 +; or 
 +; FILE = ftp://user:password@192.168.3.1/license.txt
 +;
 +;
 +; PEEDI is shipped with license keys stored in "eep:license.txt" and 
 +; printed on a label on the bottom side of PEEDI.
 +;
 +[LICENSE]
 +FILE=eep:license.txt
 +;--------------------------------------------------------------------------
 +
 +[DEBUGGER]
 +PROTOCOL            = gdb_remote            ; gdb remote
 +REMOTE_PORT         = 2000                  ; TCP/IP port
 +
 +[TARGET]
 +PLATFORM            = ARM                   ; platform is ARM
 +
 +[PLATFORM_ARM]
 +JTAG_CHAIN          = 4                     ; list of IR length of all TAP controller in JTAG chain
 +JTAG_CLOCK          = 20, 4000              ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 4MHz for normal work
 +                                            ; Freescale recommends max JTAG_CLOCK 1/6 of the system clock
 +TRST_TYPE           = OPENDRAIN             ; type of TRST output: OPENDRAIN or PUSHPULL
 +RESET_TIME          = 20                    ; 20ms reset pulse, 0 means no reset
 +TIME_AFTER_RESET    = 100                   ; time between releasing the reset and starting the jtag communication
 +CORE0               = MAC7100               ; TAP is Freescale MAC71xx  CPU
 +CORE0_STARTUP_MODE  = RESET                 ; startup mode after reset:
 +                                            ;   if RESET than no code is executed after reset
 +                                            ;   if STOP,XX then the target executes code for XX period in ms.
 +                                            ;   if RUN then the target executes code until stopped by the telnet "halt" command
 +
 +CORE0_BREAKMODE         = soft              ; breakpoint mode:
 +                                            ; soft - software breakpiont
 +                                            ; hard - use hardware breakpoints instead of software
 +CORE0_BREAK_PATTERN     = 0xDFFFDFFF        ; software breakpoint pattern
 +
 +CORE0_INIT              = INIT_MAC7100      ; init section for MAC7100 board
 +CORE0_FLASH0            = FLASH_PROG        ; PROGRAM flash section parameters
 +CORE0_ENDIAN            = BIG               ; core is big endian
 +CORE0_WORKSPACE_ADDR    = 0x40000100        ; start address of workspace for flash programmer
 +CORE0_WORKSPACE_LEN     = 0x4000            ; length of workspace in bytes
 +
 +CORE0_LOCKOUT_RECOVERY  = 19                ; If this parameter is present, PEEDI automatically executes a
 +                                            ; "JTAG Lockout Recovery" procedure during reset processing
 +                                            ; if the MAC7100 flash is secured
 +                                            ; Fsys 4MHz CLKD=9; Fsys 8MHz CLKD=19
 +CORE0_FILE              = "myfile.bin", BIN, 0x40000100 ; default file
 +CORE0_PATH              = "tftp://192.168.3.1" ; default path
 +
 +[INIT_MAC7100]
 +memory write8  0xfc088004 0     ; CRGINT Disable clock interrupts
 +
 +; Speed-up to fsys = 50MHz, Fsys = 2*Fosc*(mul/div)
 +; Quartz is 8.00 MHz
 +;--------------------------------------------------
 +memory write8  0xfc088001 0x07          ; REFDV - CRG Reference Divider register - divide by 8
 +memory write8  0xfc088000 0x18          ; SYNR - CRG synthesizer Register - multiply by 25
 +wait 10
 +memory write8  0xfc088005 0x80          ; CLKSEL - Select fsys=PLLCLK
 +memory write8  0xFC088003 0x72          ; clear the flags
 +
 +memory write8  0xfc088008 0x00          ; BDMCTL - SWT and RTI keep running in debug mode
 +memory write16 0xfc0e80c4 0x0080        ; output CLKOUT on PD2
 +
 +set pc 0x40000000                       ; set PC to RAM memory base
 +
 +[FLASH_PROG]
 +CHIP                = MAC7100           ; flash chip
 +CPU_CLOCK           = 50000             ; PLL clock
 +CHECK_ID            = YES
 +FILE                = "myprog.bin", BIN, 0xFC100000 ; file to program
 +AUTO_ERASE          = NO               ; erase before program
 +
 +
 +
 +[SERIAL]                                ; serial port configuration
 +BAUD                = 115200
 +STOP_BITS           = 1
 +PARITY              = NONE
 +TCP_PORT            = 0                 ; enable CLI over RS232
 +;TCP_PORT           = 2023              ; enable serial over TCP/IP
 +
 +[TELNET]
 +PROMPT              = "MAC7100> "       ; telnet prompt
 +;BACKSPACE          = 127               ; comment out for autodetect
 +
 +[DISPLAY]
 +BRIGHTNESS          = 20                ; LED indicator brightness
 +VOLUME              = 25                ; zummer volume
 +
 +[ACTIONS]                               ; user defined scripts
 +1 = erase
 +2 = prog
 +3 = dump_ram
 +4 = dump_flash
 +
 +[erase]                                 ; erase flash
 +flash erase
 +
 +[prog]                                  ; program flash
 +flash prog
 +</code>
 +
 +=== ... ===
  
 <code> <code>
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 ; mass erase does erase program and data flash. ; mass erase does erase program and data flash.
 </code> </code>
- 
  
  
  • artikel/ipc/mac7116.txt
  • Zuletzt geändert: Thu. 11.11.2021 07:32
  • von go4it