Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Beide Seiten der vorigen Revision Vorhergehende Überarbeitung Nächste Überarbeitung | Vorhergehende Überarbeitung Nächste ÜberarbeitungBeide Seiten der Revision | ||
artikel:ipc:mac7116 [Mon. 01.04.2019 04:00] – go4it | artikel:ipc:mac7116 [Mon. 01.04.2019 13:29] – go4it | ||
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* Quartz: 8 MHz | * Quartz: 8 MHz | ||
* Program Flash: 1 MByte | * Program Flash: 1 MByte | ||
- | * Data Flash: | + | * Data Flash: |
- | * SRAM: 32 KByte | + | * SRAM: 48 KByte |
* Datenblatt: [[https:// | * Datenblatt: [[https:// | ||
Zeile 69: | Zeile 69: | ||
* http:// | * http:// | ||
* https:// | * https:// | ||
+ | |||
+ | ==== External Interface Module (EIM) Configuration Registers ==== | ||
+ | |||
+ | Address range: 0xFC00 8000 – 0xFC00 BFFF | ||
+ | |||
+ | ==== CFM Flash Configuration Field ==== | ||
+ | |||
+ | ^ Address Offset from PROGRAM FLASH BASE ^ Size ^ Function ^ Factory Default ^ | ||
+ | | 0x0400 – 0x0407 | 8 | Backdoor Comparison Key | 0xFFFF_FFFF_FFFF_FFFF | | ||
+ | | 0x0408 – 0x040B | ||
+ | | 0x040C – 0x040F | ||
+ | | 0x0410 – 0x0413 | ||
+ | | 0x0414 – 0x0417 | ||
+ | | 0x0418 | ||
+ | | 0x0419 | ||
+ | | 0x041A | ||
==== CFM Registers and values ==== | ==== CFM Registers and values ==== | ||
- | === CFMCLKD === | + | Address Range: 0xFC0F 0000 – 0xFC0F 3FFF |
+ | |||
+ | === CFM Clock Divider Register (CFMCLKD) === | ||
- | * Memory Address: | ||
^ Register | ^ Register | ||
- | | CFMCLKD | 0xFC0F0002 | + | | CFMCLKD | 0xFC0F 0002 | 8 Bits | |
+ | The CFMCLKD register is used to control the period of the clock used for timed events in program anderase algorithms. All CFMCLKD register bits are readable while bits [6:0] are write once and bit 7 is notwritable. | ||
- | ==== CFM-Command "Mass Erase Flash" (0x41) | + | **The CFMCLKD register bits PRDIV8 and DIV must be set with appropriate values before programming or erasing the CFM Flash memory.** |
+ | |||
+ | === CFM-Command "Mass Erase Flash" (0x41) === | ||
{{: | {{: | ||
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https:// | https:// | ||
+ | |||
+ | === DEFs === | ||
< | < | ||
Zeile 104: | Zeile 126: | ||
cfmdfdacc | cfmdfdacc | ||
</ | </ | ||
+ | |||
+ | === Segger === | ||
< | < | ||
Zeile 113: | Zeile 137: | ||
mem16 fe000000,1 // verify writing-> | mem16 fe000000,1 // verify writing-> | ||
</ | </ | ||
+ | |||
+ | === PEEDI === | ||
+ | |||
+ | < | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; PEEDI target configuration file for Freescale MAC7100 processor | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; The software is delivered "AS IS" without warranty or condition of any | ||
+ | ; kind, either express, implied or statutory. This includes without | ||
+ | ; limitation any warranty or condition with respect to merchantability or | ||
+ | ; fitness for any particular purpose, or against the infringements of | ||
+ | ; intellectual property rights of others. | ||
+ | ; | ||
+ | ; | ||
+ | |||
+ | ; | ||
+ | ; The following section contains licenses that are required for PEEDI to | ||
+ | ; operate. These licenses must be filled before using this file. | ||
+ | ; The [LICENSE] section may contain license keys for one or more PEEDIs. | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; The [LICENSE] section may point to an external file which contains | ||
+ | ; license keys for one or more PEEDIs. The external file must include | ||
+ | ; the text [LICENSE] followed by all keys. | ||
+ | ; | ||
+ | ; | ||
+ | ; | ||
+ | ; FILE = tftp:// | ||
+ | ; or | ||
+ | ; | ||
+ | ; or | ||
+ | ; FILE = ftp:// | ||
+ | ; | ||
+ | ; | ||
+ | ; PEEDI is shipped with license keys stored in " | ||
+ | ; printed on a label on the bottom side of PEEDI. | ||
+ | ; | ||
+ | [LICENSE] | ||
+ | FILE=eep: | ||
+ | ; | ||
+ | |||
+ | [DEBUGGER] | ||
+ | PROTOCOL | ||
+ | REMOTE_PORT | ||
+ | |||
+ | [TARGET] | ||
+ | PLATFORM | ||
+ | |||
+ | [PLATFORM_ARM] | ||
+ | JTAG_CHAIN | ||
+ | JTAG_CLOCK | ||
+ | ; Freescale recommends max JTAG_CLOCK 1/6 of the system clock | ||
+ | TRST_TYPE | ||
+ | RESET_TIME | ||
+ | TIME_AFTER_RESET | ||
+ | CORE0 = MAC7100 | ||
+ | CORE0_STARTUP_MODE | ||
+ | ; if RESET than no code is executed after reset | ||
+ | ; if STOP,XX then the target executes code for XX period in ms. | ||
+ | ; if RUN then the target executes code until stopped by the telnet " | ||
+ | |||
+ | CORE0_BREAKMODE | ||
+ | ; soft - software breakpiont | ||
+ | ; hard - use hardware breakpoints instead of software | ||
+ | CORE0_BREAK_PATTERN | ||
+ | |||
+ | CORE0_INIT | ||
+ | CORE0_FLASH0 | ||
+ | CORE0_ENDIAN | ||
+ | CORE0_WORKSPACE_ADDR | ||
+ | CORE0_WORKSPACE_LEN | ||
+ | |||
+ | CORE0_LOCKOUT_RECOVERY | ||
+ | ; "JTAG Lockout Recovery" | ||
+ | ; if the MAC7100 flash is secured | ||
+ | ; Fsys 4MHz CLKD=9; Fsys 8MHz CLKD=19 | ||
+ | CORE0_FILE | ||
+ | CORE0_PATH | ||
+ | |||
+ | [INIT_MAC7100] | ||
+ | memory write8 | ||
+ | |||
+ | ; Speed-up to fsys = 50MHz, Fsys = 2*Fosc*(mul/ | ||
+ | ; Quartz is 8.00 MHz | ||
+ | ; | ||
+ | memory write8 | ||
+ | memory write8 | ||
+ | wait 10 | ||
+ | memory write8 | ||
+ | memory write8 | ||
+ | |||
+ | memory write8 | ||
+ | memory write16 0xfc0e80c4 0x0080 | ||
+ | |||
+ | set pc 0x40000000 | ||
+ | |||
+ | [FLASH_PROG] | ||
+ | CHIP = MAC7100 | ||
+ | CPU_CLOCK | ||
+ | CHECK_ID | ||
+ | FILE = " | ||
+ | AUTO_ERASE | ||
+ | |||
+ | |||
+ | |||
+ | [SERIAL] | ||
+ | BAUD = 115200 | ||
+ | STOP_BITS | ||
+ | PARITY | ||
+ | TCP_PORT | ||
+ | ; | ||
+ | |||
+ | [TELNET] | ||
+ | PROMPT | ||
+ | ; | ||
+ | |||
+ | [DISPLAY] | ||
+ | BRIGHTNESS | ||
+ | VOLUME | ||
+ | |||
+ | [ACTIONS] | ||
+ | 1 = erase | ||
+ | 2 = prog | ||
+ | 3 = dump_ram | ||
+ | 4 = dump_flash | ||
+ | |||
+ | [erase] | ||
+ | flash erase | ||
+ | |||
+ | [prog] | ||
+ | flash prog | ||
+ | </ | ||
+ | |||
+ | === ... === | ||
< | < | ||
Zeile 311: | Zeile 483: | ||
</ | </ | ||
- | |||
- | === CFM Clock Divider Register (CFMCLKD) === | ||
- | |||
- | The CFMCLKD register is used to control the period of the clock used for timed events in program anderase algorithms. All CFMCLKD register bits are readable while bits [6:0] are write once and bit 7 is notwritable. | ||
- | |||
- | **The CFMCLKD register bits PRDIV8 and DIV must be set with appropriate values before programming or erasing the CFM Flash memory.** | ||